BNK4_EN=BNK4_EN_0, BNK1_EN=BNK1_EN_0, BNK2_EN=BNK2_EN_0, SRAM_RDY=SRAM_RDY_0, BNK5_EN=BNK5_EN_0, BNK7_EN=BNK7_EN_0, BNK3_EN=BNK3_EN_0, BNK6_EN=BNK6_EN_0
SRAM Bank Enable Register
| BNK0_EN | SRAM Bank0 enable |
| BNK1_EN | SRAM Bank1 enable 0 (BNK1_EN_0): Disables Bank1 of the SRAM 1 (BNK1_EN_1): Enables Bank1 of the SRAM |
| BNK2_EN | SRAM Bank1 enable 0 (BNK2_EN_0): Disables Bank2 of the SRAM 1 (BNK2_EN_1): Enables Bank2 of the SRAM |
| BNK3_EN | SRAM Bank1 enable 0 (BNK3_EN_0): Disables Bank3 of the SRAM 1 (BNK3_EN_1): Enables Bank3 of the SRAM |
| BNK4_EN | SRAM Bank1 enable 0 (BNK4_EN_0): Disables Bank4 of the SRAM 1 (BNK4_EN_1): Enables Bank4 of the SRAM |
| BNK5_EN | SRAM Bank1 enable 0 (BNK5_EN_0): Disables Bank5 of the SRAM 1 (BNK5_EN_1): Enables Bank5 of the SRAM |
| BNK6_EN | SRAM Bank1 enable 0 (BNK6_EN_0): Disables Bank6 of the SRAM 1 (BNK6_EN_1): Enables Bank6 of the SRAM |
| BNK7_EN | SRAM Bank1 enable 0 (BNK7_EN_0): Disables Bank7 of the SRAM 1 (BNK7_EN_1): Enables Bank7 of the SRAM |
| SRAM_RDY | SRAM ready 0 (SRAM_RDY_0): SRAM is not ready for accesses. Banks are undergoing an enable or disable sequence, and reads or writes to SRAM are stalled until the banks are ready 1 (SRAM_RDY_1): SRAM is ready for accesses. All SRAM banks are enabled/disabled according to values of bits 7:0 of this register |